RISC-V is a LICENSE licensed RISC [[ISA|instruction set]] developed by ENTITY. - Specification - Documentation > QUOTE # Notability The first major, modern, open source CPU architecture. ## Implementations - [[QEMU - virtual machine]] - https://wiki.qemu.org/Documentation/Platforms/RISCV - https://github.com/LekKit/rvvm - https://github.com/riscv-software-src/riscv-isa-sim - https://github.com/d0iasm/rvemu - runs [[xv6]] - https://github.com/fwsGonzo/libriscv # Instruction Set It is very similar to [[MIPS]]. ## Complexity ## Features # History # Resources - [[RISC-V Dev Boards and SBCs]] - GNU Toolchain (binutils, gcc) plus extras (LLVM, musl, newlib) - https://github.com/riscv-collab/riscv-gnu-toolchain - Simulator with stepping and register inspection - https://creatorsim.github.io/creator/ - https://github.com/riscv-software-src/riscv-pk # References - https://github.com/mikeroyal/RISC-V-Guide ## Instruction Sets - https://risc-v.guru/instructions/ - https://devopedia.org/risc-v-instruction-sets ## Emulators - https://github.com/d0iasm/rvemu-for-book - https://www.riscfive.com/risc-v-simulators/ - https://riscv-programming.org/simulator.html - https://github.com/DavidBurela/riscv-emulator-docker-image