RISC-V is a LICENSE licensed RISC [[ISA|instruction set]] developed by ENTITY. - Specification - Documentation > QUOTE # Notability The first major, modern, open source CPU architecture. ## Implementations - [[QEMU - virtual machine]] - https://wiki.qemu.org/Documentation/Platforms/RISCV - https://github.com/LekKit/rvvm - https://github.com/riscv-software-src/riscv-isa-sim - https://github.com/d0iasm/rvemu - runs [[xv6]] - https://github.com/fwsGonzo/libriscv # Instruction Set It is very similar to [[MIPS]]. ## Complexity The base instruction set contains only 47 instructions. Most of these instructions are actually 12-bit operations, no joke. With dedicated instructions for the upper 20 bits to perform awkward 32 bit operations. Truly bizarre. ## Features ## Architectures ### RV32I The default 32-bit integer core with 32 registers. The `x0` register is like `/dev/null`, always reads as zero and ignores any value written to it. ### RV32E As above but with only 15 registers. Intended for low cost embedded microprocessors. ## Extensions ### I Extension Basic integer instructions. ### M Extension Integer multiplication and division. ### A Extension Atomic memory operations. ### F Extension 32-bit single precision floating point. ### D Extension 64-bit double precision floating point. ### Q Extension 128-bit quad precision floating point. ### C Extension 16-bit instruction set for integers and memory alignments. (May also cover other extensions) ### Zicsr https://five-embeddev.com/riscv-user-isa-manual/Priv-v1.12/csr.html ### Zifencei https://five-embeddev.com/riscv-user-isa-manual/Priv-v1.12/zifencei.html ## Configurations ### G Configuration The "general" configuration which includes each of the IMAFD extensions. # History # Resources - [[RISC-V Dev Boards and SBCs]] - GNU Toolchain (binutils, gcc) plus extras (LLVM, musl, newlib) - https://github.com/riscv-collab/riscv-gnu-toolchain - Simulator with stepping and register inspection - https://creatorsim.github.io/creator/ - https://github.com/riscv-software-src/riscv-pk # References - https://github.com/mikeroyal/RISC-V-Guide ## Instruction Sets - https://web.archive.org/web/20250124143244/https://risc-v.guru/instructions/ - https://msyksphinz-self.github.io/riscv-isadoc/html/index.html - https://devopedia.org/risc-v-instruction-sets - https://dzone.com/articles/introduction-to-the-risc-v-architecture ## Emulators - https://github.com/d0iasm/rvemu-for-book - https://www.riscfive.com/risc-v-simulators/ - https://riscv-programming.org/simulator.html - https://github.com/DavidBurela/riscv-emulator-docker-image