Xtensa is a proprietary RISC-style instruction set architecture designed by Tensilica - who was later acquired by Cadence. - [Website](https://www.cadence.com/en_US/home/tools/ip/tensilica-ip/tensilica-xtensa-controllers-and-extensible-processors.html) > Xtensa processors are based on a modular, highly flexible 32-bit RISC architecture that can easily scale from a tiny, cache-less controller or task engine to a high-performance SIMD/VLIW DSP. # Notability # Philosophy # OS Support This chip is primarily expected to be used bare metal, but there are some operating systems which support the platform: - [[FreeRTOS]] - [[Zephyr]] > The Esp32 has more power, and more memory, than a PC in the early 90’s, and RTOS is a lot better than DOS! It easily handles quite a few threads – my current main project has 15 – and can handle a surprising large project… \- via [Hackaday Commenter](https://hackaday.com/2023/05/10/tiny-microcontroller-uses-real-time-operating-system/#comment-6641511) # Features - Modern base ISA with 80 RISC instructions for true compatibility across every Xtensa processor - Xtensa ISA has been backwards compatible since its introduction in 1998 - Xtensa ISA is fundamentally architected for extensibility - Many available pre-verified optional blocks - Any differentiating designer-defined instructions written since 1998 can still be re-used today # References See also documentation in [[External]]/Sync/Library/Programming-Computers/ ```cardlink url: https://github.com/espressif/xtensa-isa-doc title: "GitHub - espressif/xtensa-isa-doc" description: "Contribute to espressif/xtensa-isa-doc development by creating an account on GitHub." host: github.com favicon: https://github.githubassets.com/favicons/favicon.svg image: https://opengraph.githubassets.com/f138e661b6e86b828a311d12df0b52a3b3c26699b64a50680421c8d1401935cc/espressif/xtensa-isa-doc ``` ```cardlink url: https://hackaday.com/2023/05/10/tiny-microcontroller-uses-real-time-operating-system/ title: "Tiny Microcontroller Uses Real-Time Operating System" description: "Most of the computers we interact with on a day-to-day basis use an operating system designed for flexibility. While these are great tools for getting work done or scrolling your favorite sites, th…" host: hackaday.com image: https://hackaday.com/wp-content/uploads/2023/05/esp32-home.jpg ``` ```cardlink url: https://www.zephyrproject.org/zephyr-rtos-on-esp32/ title: "Zephyr RTOS on ESP32 - Zephyr Project" host: www.zephyrproject.org favicon: https://www.zephyrproject.org/wp-content/uploads/sites/38/2023/04/cropped-zephyr_logo_r_color_negative_minimum-32x32.png image: https://miro.medium.com/max/283/1*29MFNYBkDFWU8jQdf-lE7g.png ``` ```cardlink url: https://www.tutorialspoint.com/esp32_for_iot/esp32_for_iot_setting_up_rtos_for_dual_core_and_multi_threaded_operation.htm title: "Setting up RTOS for dual-core & multi-threaded operation" description: "Setting up RTOS for dual core multi threaded operation - A key feature of ESP32 that makes it so much more popular than its predecessor, ESP8266, is the presence of two cores on the chip. This means that we can have two processes executing in parallel on two different cores. Of course, you can argue that parallel operation can also be achieved on a sing" host: www.tutorialspoint.com favicon: /favicon.ico image: https://www.tutorialspoint.com/images/tp_big_logo.png ``` # Data Sheets https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ip/tensilica-ip/tip-xtensa-lx-pb.pdf ## LX6 Used by some [[ESP32]] SoCs. https://mirrobo.ru/wp-content/uploads/2016/11/Cadence_Tensillica_Xtensa_LX6_ds.pdf ## LX7 Used by some [[ESP32]] SoCs.