# ARMv4T Assembly ## Assembly code syntax The general structure of each line of assembly code is: ```armasm <label> <instruction/directive/pseudo-instruction> <operand 1>{, operands...} ``` - *Label* - memory addresses that can be used like *pointers*. They are *not preceded* by *horizontal* whitespace. ^4c8f9c - *Instructions* - instructions from the ARMv4T architecture. - [[ARMv4T Assembly Directives|Directives]] - instructions for the assembler. - [[ARMv4T Assembly Pseudo-Instructions|Pseudo-instructions]] - instructions that are easier to program with and are translated by the assembler to real instructions. - *Operands* - values on which the instructions operate on. Instructions, directives, and pseudo-instructions must be *preceded* by *horizontal* whitespace. > [!Example]- > ```armasm > AREA program, CODE, READONLY > ENTRY > > MOV r0, 5 > MOV r1, r0 > MOV r2, r1 > > stop B stop > > END > ``` > - `AREA`, `ENTRY`, and `END` are *directives*. > - `MOV` and `B` are *instructions*. > - `R0`, `R1`, `R2`, and the number `5` are *operands*. > - `stop` is a *label*. ## Literal constants Literal constants are preceded by a `#` unless they are an operand of a *directive*. - *Number* - Decimal - `255` - Hexadecimal - `0x255` - Any other base from *2 to 9* in the form `n_xxxx` - `2_10101010` - *Character* - `'A'` - *Null-terminated string* - `"Hello World"` Literal constants can be up to 32-bits in size and may require the use of a [[ARMv4T Assembly#Pseudo-instructions|pseudo-instruction]] to be used as an operand. ## Conditional execution Conditional execution can be applied to an instruction by adding a [[ARM Instruction Encoding#^e9df96|two-letter suffix]] to the operation code. The [[Arithmetic Logic Unit#Status flags|conditional flags]] in the [[ARM7TDMI#Program status registers|CPSR]] are updated after the following instructions are executed: - Data processing instructions with the `S` option. - Flag-setting instructions: `CMP`, `CMN`, `TST`, `TEQ`. - Shift operations: `LSL`, `LSR`, `ASR`, `ROR`, `RRX`. - Special instructions that edit CPSR bits. ## Data processing instructions There are three forms of syntax for [[ARM Instruction Encoding#^97daa4|data processing instructions]]. For operations `MOV` and `MVN`: ```armasm <opcode>{cond}{S} <Rd>, <operand2> ``` For operations `CMP`, `CMN`, `TST`, and `TEQ`: ^573221 ```armasm <opcode>{cond} <Rd>, <operand2> ``` Note the absence of the `S` option, since these instructions *always* updates condition codes. For operations `ADD`, `SUB`, `RSB`, `ADC`, `SBC`, `RSC`, `AND`, `BIC`, `EOR` and `ORR`: ```armasm <opcode>{cond}{S} <Rd>, <Rn>, <operand2> ``` - `cond` - [[ARMv4T Assembly#Conditional execution|condition]] for execution. - `S` - sets the instruction to *update condition codes*. - `Rd` - the *destination* register. - `Rn` - the first *source* operand register. - `operand2` - either an immediate, register, shifted register, or rotated register. Refer to [[ARM Instruction Encoding#Data processing operands|data processing operands]]. - `#<immediate>` - an immediate value. - `<Rm>` - a register. - `<Rm>, <shift> <#shift_imm>` - a register `Rm` shifted or rotated by an immediate value `shift_imm` using the shift type `shift`. - `<Rm>, <shift> <Rs>` - a register `Rm` shifted or rotated by a register value `Rs` using the shift type `shift`. ## Load and store word or unsigned byte instructions The typical [[ARM Instruction Encoding#Pre-indexed addressing|pre-indexed]] load/store instruction syntax is: ```armasm <opcode>{cond} <Rd> [<Rn>, <offset>]{!} ``` - `opcode` - the operation. - `LDR` for loading. - `STR` for storing. - `cond` - [[ARMv4T Assembly#Conditional execution|condition]] for execution. - `Rd` - the *destination* register. - `Rn` - the *base register*. - `offset` - either an immediate, register, shifted register, or rotated register. Refer to [[ARM Instruction Encoding#Offsets|offsets]]. - `#+/-<offset_12>` - an immediate 12-bit value. - `+/- <Rm>` - a register. - `+/- <Rm>, <shift> <#shift_imm>` - a register `Rm` shifted or rotated by an immediate value `shift_imm` using the shift type `shift`. - `!` - sets the instruction to *write back* the target address to the base register after the load/store operation. The typical [[ARM Instruction Encoding#Post-indexed addressing|post-indexed]] load/store instruction syntax is: ```armasm <opcode>{cond} <Rd> [<Rn>], <offset> ``` ## Branch instructions The syntax of branch and branch and link is: ```armasm B{L}{<cond>} <target_address> ``` - `L` - set the branch to also link, causing the resulting instruction to store a *return address* in the link register `R14` or `LR`. - `cond` - [[ARMv4T Assembly#Conditional execution|condition]] for execution. - `target_address` - the address or [[ARMv4T Assembly#^4c8f9c|label]] to branch to. Refer to [[ARM Instruction Encoding#^6b6334|the calculation of the target address]].