# ARM7TDMI **ARM7, 16 bit Thumb, JTAG Debug, fast Multiplier, enhanced ICE** The **ARM7TDMI** is a *32-bit* [[Instruction Set Architecture#^886a94|RISC]] processor core which implements the [[ARMv4T Assembly|ARMv4T]] instruction set. ARM is [[load-store architecture]]. [[ARM Instruction Encoding|ARM instructions]] are *32-bits* wide and thus a word is defined as 32-bits. ARM memory is *byte-addressed* and the address and data [[Bus|buses]] are 32-bit wide. ![[ARM7TDMICore.svg]] >[!Core signals]- | Symbol | Name | | ------- | -------------------- | | A[31:0] | Address bus | | ABE | Address bus enable | | ALE | Address latch enable | | D[31:0] | Data bus | | DBE | Data bus enable | | nENIN | NOT enable input | | nENOUT | NON enable output | ## Processor modes The ARM7TDMl has *seven* processor modes: 6 privileged modes and 1 unprivileged mode. The only *unprivileged* mode is the *user* mode, which is the usual ARM program execution state and is used for most applications. | Mode | Description | | ---------------- | ------------------------------------------------------------------------------------- | | Supervisor (SVC) | Entered upon *CPU reset* or when a *Software Interrupt* (SWI) instruction is executed | | FIQ | Entered when a *fast/high priority* interrupt request is accepted | | IRQ | Entered when a *slow/low priority* interrupt request is accepted | | Abort | Entered when a *prefetch* or *data abort* exception (memory access violation) occurs | | Undefined | Entered when an *undefined instruction* exception occurs | | System | A privileged mode using the *same registers* as User mode | ## Registers The ARM7TDMI has *37* registers of *32-bits*: - 30 general purpose - 6 status - 1 program counter The 30 general purpose registers are only numbered up to `R15` which includes the *banked registers*, registers which are *physically distinct* from similarly numbered registers which are dedicated to specific *processor modes*. The following general purpose registers are also aliased: - `R13` - SP, stack pointer - `R14` - LR, link register - `R15` - PC, program counter At any given time, *only 15* general purpose registers `R0 - R14`, the program counter `R15`, and one or two status registers can be accessed. ### General purpose registers Banked registers are shown below in italics. | User and System | FIQ | IRQ | Supervisor | Abort | Undefined | |:---------------:|:-----------:|:---------:|:----------:|:-----:|:---------:| | `R0` | `R0` | `R0` | `R0` | `R0` | `R0` | | `R1` | `R1` | `R0` | `R0` | `R0` | `R0` | | `R2` | `R2` | `R0` | `R0` | `R0` | `R0` | | `R3` | `R3` | `R0` | `R0` | `R0` | `R0` | | `R4` | `R4` | `R0` | `R0` | `R0` | `R0` | | `R5` | `R5` | `R0` | `R0` | `R0` | `R0` | | `R6` | `R6` | `R0` | `R0` | `R0` | `R0` | | `R7` | `R7` | `R0` | `R0` | `R0` | `R0` | | `R8` | *`R8_fiq`* | `R0` | `R0` | `R0` | `R0` | | `R9` | *`R9_fiq`* | `R0` | `R0` | `R0` | `R0` | | `R10` | *`R10_fiq`* | `R0` | `R0` | `R0` | `R0` | | `R11` | *`R11_fiq`* | `R0` | `R0` | `R0` | `R0` | | `R12` | *`R12_fiq`* | `R0` | `R0` | `R0` | `R0` | | `R13` | *`R13_fiq`* | *`R13_irq`* | *`R13_svc`* | *`R13_abt`* | *`R13_und`* | | `R14` | *`R14_fiq`* | *`R14_irq`* | *`R14_svc`* | *`R14_abt`* | *`R14_und`* | | `R15` | `R15` | `R15` | `R15` | `R15` | `R15` | Note that the *program counter* is accessible in all modes and points to the instruction currently being fetched from memory. It is *incremented by 4* after each instruction fetched, since each instruction is 4 bytes or a word long. In ARM state, bits `[1:0]` of `R15` are *undefined* and bits `[31:2]` hold the program counter. ### Program status registers There are two types of the same format program status registers, the *current program status register* (CPSR) and the *saved program status register* (SPSR). The SPSR stores the current values of CPSR when an *exception* occurs and thus is only accessible in exception handling modes, i.e. not user and system mode. The program status registers contain information about the *most recently performed* [[Arithmetic Logic Unit|ALU]] operation, control the *disabling* of the *interrupts*, and set the *processor mode*. | 31 | 30 | 29 | 28 | 27 | ... | | :--: | :--: | :--: | :--: | :--: | :--: | | N | Z | C | V | - | ... | | ... | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: | | ... | - | I | F | T | M4 | M3 | M2 | M1 | M0 | - [[Arithmetic Logic Unit#Status flags|Conditional flag]] bits `[31:28]` - *I* - disable IRQs - *F* - disable FIQs - *T* - Thumb instruction enable - Processor mode bits `[4:0]` | PSR[4:0] | Mode | |:--------:|:----------:| | `10000` | User | | `10001` | FIQ | | `10010` | IRQ | | `10011` | Supervisor | | `10111` | Abort | | `11011` | Undefined | | `11111` | System | ## Instruction pipeline The ARM7TDMI is a *3-stage pipeline* architecture: fetch, decode, execute. ![[3StagePipeline.svg]] This pipeline means that at the point of execution of an instruction, the *program counter* contains the *address of the instruction + 8 bytes*[^1]. [^1]: ARM instructions are _32-bits or 4 bytes_ wide.